1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to integrated circuits comprising static random-access memory devices.
2. Description of the Related Art
Types of semiconductor memory include dynamic random-access memory (DRAM) and static random-access memory (SRAM). DRAM devices comprise memory cells having a relatively simple structure, in particular memory cells wherein an amount of charge stored in a capacitor is used to represent a bit of information. Due to the simple structure of DRAM cells, a high density of integration can be obtained. However, due to leakage currents in the capacitors, DRAM devices typically require refresh cycles to avoid a loss of stored information.
In SRAM devices, cross-coupled inverters are used for storing information. In SRAM devices, refresh cycles need not be performed, and they typically allow a greater speed of operation than DRAM devices. However, SRAM devices comprise memory cells which typically have a more complex structure than the memory cells of DRAM devices, which may limit the density of integration that can be obtained in SRAM devices.
An SRAM device 100 will be described with reference to FIG. 1. The SRAM device 100 comprises an SRAM bitcell 101, a bitline 102 and an inverse bitline 103 connected to a bitline control circuit 127, a wordline 104 connected to a wordline control circuit 128 and a high voltage power supply line 105 and a low voltage power supply line 106 connected to a power supply control circuit 130.
In operation of the device 100, the high voltage power supply line 105 can be maintained at a higher voltage than the low voltage power supply line 106. Accordingly, the voltage of the high voltage power supply line 105 will be denoted as “high voltage” and the voltage of the low voltage power supply line 106 will be denoted as “low voltage,” although the high voltage is typically on an order of magnitude of a few volts.
The SRAM cell 101 comprises a first inverter 107 having an input 113 and an output 111, and a second inverter 108 having an input 114 and an output 112. The output 111 of the first inverter 107 is electrically connected to the input 114 of the second inverter 108, and the output 112 of the second inverter 108 is electrically connected to the input 113 of the first inverter 107.
Each of the inverters 107, 108 comprises a pull-up transistor, wherein the pull-up transistor of the first inverter 107 is denoted by reference numeral 115, and the pull-up transistor of the second inverter 108 is denoted by reference numeral 116. Moreover, each of the inverters 107, 108 comprises a pull-down transistor, wherein reference numeral 117 denotes the pull-down transistor of the first inverter 107, and reference numeral 118 denotes the pull-down transistor of the second inverter 108.
The pull-up transistors 115, 116 may be P-channel transistors, which may be switched from an on state, wherein the transistors have a relatively high conductivity, to an off state by applying the high voltage to their gate electrodes so that there is only a relatively low source drain leakage conductivity. The pull-down transistors 117, 118 may be N-channel transistors which may be switched from an off state, wherein there is only a relatively low leakage conductivity, to an on state by applying the high voltage to their gate electrodes so that they have a relatively high conductivity.
The SRAM cell 101 further comprises pass-gate transistors 109, 110. The pass-gate transistor 109 is electrically connected between the inverse bitline 103 and the output 111 of the first inverter, and the second pass-gate transistor 110 is electrically connected between the bitline 102 and the output 112 of the second inverter 108. Gate electrodes of the pass-gate transistors 109, 110 are electrically connected to the wordline 104. The pass-gate transistors 109, 110 may be N-channel transistors which may be switched from an off state to an on state by applying the high voltage to their gate electrodes. Accordingly, if the high voltage is applied to the wordline 104, an electrical connection is established between the inverse bitline 103 and the output 111 of the first inverter 107, and between the bitline 102 and the output 112 of the second inverter 108.
The device 100 may comprise a plurality of SRAM cells having a structure corresponding to the structure of SRAM cell 101, and may also comprise a plurality of wordlines similar to wordline 104, and a plurality of bitlines and inverse bitlines similar to bitline 102 and inverse bitline 103. Typically, there is an array of SRAM cells having rows and columns of SRAM cells, wherein the wordlines extend along the rows of the array, and the bitlines and inverse bitlines extend along the columns of the array. Individual SRAM cells of the device 100 can be addressed by applying the high voltage to the wordline to which the SRAM cell is connected to switch the pass-gate transistors of the respective cell into the on state and by applying and/or reading voltages from the bitline and the inverse bitline to which the SRAM cell is connected. The other wordlines can be maintained at the low voltage. Bitlines and inverse bitlines are typically kept at the high voltage during standby mode and are left electrically floating during reading.
The SRAM cell 101 can have three modes of operation. In a standby mode, the voltage of wordline 104 is low, so that pass-gate transistors 109, 110 are in the off state and the inverters 107, 108 are electrically disconnected from bitline 102 and inverse bitline 103. Since the output 111 of the first inverter 107 is electrically connected to the input 114 of the second inverter 108, and the output 112 of the second inverter 108 is electrically connected to the input 113 of the first inverter 107, the inverters 107, 108 can reinforce each other, so that they substantially maintain their respective state. Accordingly, there is a first state of the SRAM cell 101, wherein the output 111 of the first inverter 107 is substantially at the low voltage and the output 112 of the second inverter 108 is substantially at a the high voltage, and a second state, wherein the output 111 of the first inverter 107 is substantially at the high voltage, and the output 112 of the second inverter 108 is substantially at the low voltage. These two states can be used to store one bit of information.
For reading the bit of information stored in the SRAM cell 101, the bitline 102 and the inverse bitline 103 can be pre-charged to the high voltage. Then, the bitline 102 and the inverse bitline 103 are left electrically floating and the wordline 104 is switched from low voltage to high voltage, so that the pass-gate transistors 109, 110 establish an electrical connection between the bitline 102 and the output 112 of the second inverter 108, and an electrical connection between the inverse bitline 103 and the output 111 of the first inverter 107. Depending on the state of the SRAM cell 101, a voltage difference between the bitline 102 and the inverse bitline 103 is created, which can be sensed by a sense amplifier 129 arranged in the bitline control circuit 127 to determine the state of SRAM cell 101.
For writing data to the SRAM cell 101, the high voltage can be applied to one of the bitline 102 and the inverse bitline 103, and the low voltage can be applied to the other one of the bitline 102 and the inverse bitline 103, depending on the state of the SRAM cell 101 to be obtained after the write operation. The corresponding data signals may be applied by a write driver circuit 125 arranged in the bitline control circuit 127. Thereafter, the voltage of the wordline 104 can be switched by the wordline control circuit 127 from low to high to switch the pass-gate transistors 109, 110 into the on state. Thereby, the voltages applied to the bitline 102 and the inverse bitline 103 are applied to the inputs 113, 114 of the inverters 107, 108. If the initial state of SRAM cell 101 is different from the state to be written to SRAM cell 101, this typically causes the inverters 107, 108 to change their state.
An issue in writing data to SRAM cells can be avoiding a write failure, wherein the SRAM cells do not change its state, although the state to be written to the SRAM cells is different from the initial state. This is of particular concern for nano-scale device technologies due to a general instability of smaller SRAM cells due to an increased variation of the threshold voltages of the transistors, which is in particular caused by short channel effects and random dopant fluctuations. Writeability of SRAM cells is further affected by the reduction of the voltage of the high voltage power supply which is a further consequence of device scaling. The reduction of supply voltage reduces concurrently a write margin and a read static noise margin characterizing the ability to write and read of the SRAM cells. Consequently, a plurality of techniques has been established to improve writeability of SRAM cells.
The likelihood of a write failure occurring can be related to a ratio between a conductivity of pass-gate transistors in the on state, and a conductivity of pull-up transistors in the on state, which is denoted as “gamma ratio.” In general, a greater gamma ratio can reduce the likelihood of a write failure occurring. Accordingly, for avoiding write failures, it is advantageous if the conductivities of the pass-gate transistors in the on state (and, accordingly, a width of the channel regions of these transistors) are relatively large compared to the conductivities of the pull-up transistors 115, 116 in the on state (and, accordingly, a width of the channel regions of these transistors).
The stability of the SRAM cells with respect to a read disturbance can be dependent on the so-called “beta ratio” representing a ratio between the conductivity of pull-down transistors in the on state and the conductivity of pass-gate transistors in the on state. A greater beta ratio can be helpful for increasing the stability of SRAM cells with respect to read disturbances. Thus, it is of advantage when a width of the channel regions of the pass-gate transistors is relatively low compared to a width of the channel regions of the pull-down transistors.
Hence, there is a trade-off between the stability of SRAM cells with respect to read disturbances, and writeability of the SRAM cells, which is related to the occurrence of write failures. A greater conductivity of the pass-gate transistors in the on state may be helpful for reducing the likelihood of write failures occurring but, at the same time, may increase the likelihood of read disturbances.
For avoiding these issues, it has been proposed to modify the design of SRAM cells by separating the write and read path by including an additional port. However, such solutions typically require two additional transistors i.e., eight transistors per SRAM cell (8T-SRAM), and also require an additional read wordline per row of the device, as well as an additional read bitline per column of the device. This can substantially increase the area of the device that is required for storing one bit of information.
Thus, alternative techniques based on six-transistor-SRAM cells have been proposed to assist the write operation. These techniques are typically based on modifications of the operation signals and operation voltages during the write process. The strength of the pull-up transistors may be optimized for the read operation, whereas the resulting deteriorated write characteristics may be compensated by write assist techniques. Known write assist techniques use, for example, wordline boost, negative bitline or power supply voltage reduction schemes.
In wordline boost schemes, a voltage higher than the power supply voltage is applied to the wordlines which assist the bit cell to flip during a write operation. The boost increases the gate source voltage of the pass-gate transistor and hence increases its drive strength. The increased drive strength of the pass-gate transistor supports significantly a transition of the bitcell. The boost voltage can be routed as a separate power supply or it can be generated internally by a charge bump technique or by capacitive coupling. The benefits of this write assist scheme increases significantly as the supply voltage is scaled down.
In negative bitline schemes, a negative voltage is applied to the source of the pass-gate transistor to increase also the gate source voltage of the pass-gate transistor and to increase its drive strength. The approach of negative bitline based write assist swings the bitline voltage below zero during the write operation. Similar to the wordline boosting, the negative bitline voltage can be generated internally by a charge bump technique or by using a capacitive coupling technique.
Power supply voltage reduction schemes may be established with an enable function that allows reducing a high voltage provided by a power supply to SRAM cells during a write operation. In this case, the data writing circuit may easier overpower pull-up transistors of the SRAM cells. Thus, during the write operation, the influence of device targeting on the writeability of the SRAM cell can be eliminated or at least reduced. Disadvantageously, data corruption may occur in SRAM cells connected to unselected wordlines during the write operation. During a read operation, wherein data are read from the device, the power supply can remain at the high supply voltage.
The write assist techniques wordline boost, negative bitline or power supply voltage reduction schemes may also be combined to improve writeability of the SRAM cells. This adversely affects, however, the control signal timing as a timing critical behavior is in general a disadvantage of known write assist techniques.
A different approach to improve writeability of the SRAM cells may be based on the back gate biasing capability of fin field effect transistors (FinFETs). FinFETs have in general the potential to allow for further device scaling due to the particular characteristics of transistors formed on the basis of thin fins. FinFETs comprise well-defined channel regions and gate electrodes that may control the channel efficiently from different sides of the fin. FinFETs may be manufactured with separated front- and backgates which allows, for example, a threshold voltage tuning of the transistors by backgate biasing, i.e., by applying an appropriate bias voltage to the backgates. Consequently, backgate biasing may be used to improve writeability of SRAM cells based on FinFET architectures. Back gate biasing techniques based on FinFETs are known from U.S. Patent Publication Nos. 2006/0274569, and 2010/0188889 and U.S. Pat. No. 8,144,501. Disadvantageously, SRAM devices based on FinFETs require complex manufacturing methods. In particular, multi fin transistors may be required to adapt the “transistor-width”-ratio of pull-up and pass-gate transistors of SRAM cells as described above.
Back gate biasing has been employed also to improve writeability of SRAM cells based on fully depleted silicon on insulator (FDSOI) FET architectures. FDSOI-FET comprise a thin silicon channel layer formed on a buried oxide layer. Thus, the channel of a FDSOI-FET is not directly accessible by a back-gate electrode as the buried oxide layer may impede an access from the backside, i.e., from the substrate side. Reducing the thickness of the buried oxide layer allows, however, improving the accessibility and hence the controllability by a back gate formed in the substrate below the channel region of the FDSOI-FET.
Kim et al., “Stable High-Density FD/SOI SRAM with Selective Back-Gate Bias Using Dual Buried Oxide,” 2008 IEEE International SOI Conference Proceedings, pp. 37-38, discloses FDSOI SRAM cells comprising FDSOI-PFET pull-up transistors with thin buried oxide and FDSOI-NFET pull-down and pass-gate transistors with thick buried oxide so that the PFET pull-up transistors may be differently biased than the NFETs although a global substrate bias voltage is applied to the FDSOI SRAM device.
Grenouillet, et al., “UTBB FDSOI transistors with dual STI for a multi-Vt strategy at 20 nm node and below,” IEDM 2012, pp 64-67, discloses FDSOI SRAM cells comprising FDSOI-PFET pull-up transistors and FDSOI-NFET pull-down and pass-gate transistors separated by deep isolation trenches so that a wider backbias voltage range is applicable, which allows for more efficient device tuning.
In view of the situation described above, the present disclosure is related to a method of writing data to an array of SRAM cells and a device comprising a plurality SRAM cells that allows to obtain a relatively high stability with respect to disturbances and a relatively low likelihood of write failures occurring, while substantially avoiding or at least reducing an increase of the area of the device required for storing one bit of information.